The present invention relates to a method of producing an insulated gate bipolar transistor ("IGBT") or a vertical insulated gate field effect transistor.
Of the insulated gate field effect transistors, insulated gate bipolar transistors and power MOSFETs have substantially the same fundamental element structure in spite of a difference in detailed dimensions. The two MOSFETs are distinguished from each other depending upon whether they have on the drain side a region of an opposite conductivity type to that of the source. Therefore, IGBTs are mainly described in this specification but the same is applicable to power MOSFETs.
FIG. 3 is a sectional view showing the structure of an IGBT having an N-type channel element. Fundamentally, an IGBT has a four-layer construction of PNPN, although NPNP types can also be made. Such an IGBT includes a high-resistance N.sup.- layer 1, a P.sup.+ region 2, a P-type base region 3, a high-impurity- density P.sup.++ region 4, an N.sup.+ source region 5, a gate oxide film 6, a polysilicon gate 7, a P.sup.+ layer 8, a PSG insulation layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The symbols S, G and D represent the terminals of a source, a gate and a drain, respectively. The P.sup.+ layer 8 exists in an IGBT but does not exist in a power MOSFET.
In the region directly under the source electrode of an IGBT or a power MOSFET, it is necessary to short-circuit the N.sup.+ source region 5 and the P.sup.+ region 2, as shown in FIG. 3. Various processes are adopted for producing the short-circuited portion.
FIG. 4 shows an example of these processes for an IGBT. The same numerals are provided for the elements which are the same as those in FIG. 3. In FIG. 4, the well known initial steps are omitted. The surface of a semiconductor substrate consisting of the N.sup.- layer 1 formed on the P.sup.+ layer 8 by epitaxial growth is first subjected to initial oxidization. The semiconductor substrate is photoetched so as to form a window portion at a predetermined portion thereof and boron ions are implanted through the window portion. By thermal diffusion, the P.sup.+ region 2 is formed embedded in the N.sup.- layer 1. The gate oxide film 6 is next formed and the polysilicon layer 7 which is to serve as a gate is formed thereon. FIG. 4(a) shows the polysilicon layer 7 immediately after being photoetched so as to have a window portion. Generally, boron ions are implanted again while using the etched polysilicon layer 7 as a mask, and the P-type base region 3 is formed by high-temperature driving. A resist is applied to the P-type base region 3, which is photolithographed using a photomask so as to leave a resist 13 at the central portion. In order to form the N.sup.+ source region 5, arsenic is implanted while using the resist 13 as a mask. This state is shown in FIG. 4(b). Implantation of arsenic ions is indicated with the arrows and the implanted ions are represented by the numeral 14. At the step shown in FIG. 4(c), the resist 13 is removed and an appropriate high-temperature treatment is applied to form the N.sup.+ source region 5. Thereafter, the PSG insulation layer 9 is formed, the central part of which is photoetched so as to allow a conductive metal to be deposited thereon, thereby forming the source electrode 10.
The above-described process for short-circuiting the N.sup.+ source region 5 and the P.sup.+ region 2 is adopted in a conventional IGBT or power MOSFET. In FIG. 4, the step for forming the P.sup.++ region 4 is omitted.
The process for producing an IGBT or a power MOSFET having the above-described structure, however, has the following two problems to be solved. One is that the ion implantation for forming the N.sup.+ source region 5 using a resist mask involves a risk of poor accuracy of the position of the N.sup.+ source region 5 due to inaccurate positioning of the mask. The other is that since the process requires one additional photomask, increase in the number of steps in photoetching is unavoidable.
Accordingly, it is an object of the present invention to eliminate the above-described problems in the prior art and to provide a method of producing a vertical insulated gate MOSFET having a shorted structure between an N.sup.+ source region and a P.sup.+ region by forming the N.sup.+ source region with high accuracy by self alignment without using any special mask in place of a conventional method of forming the N.sup.+ source by using a resist mask.